1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a column selection circuit of a DRAM.
2. Discussion of the Related Art
A conventional column selection circuit will be described with reference to the accompanying drawings.
FIG. 1 is a schematic view illustrating a conventional column selection circuit.
As shown in FIG. 1, the conventional column selection circuit includes a memory cell 11, a bit line sensing amplifier 13, a read bus line RI, a read bus bar line RI, a write bus line WI, a write bus bar line WI, a first data transmission portion 15, a second data transmission portion 17, a first enable signal output portion 19, a second enable signal output portion 19a, an equalizer 21, and a precharge level adjusting portion 23. The memory cell 11 stores data. The bit line sensing amplifier 13 senses the data of the memory cell 11. The read bus line RI and the read bus bar line RI transmit the data output from the bit line sensing amplifier 13 to a main sensing amplifier (not shown). The write bus line WI and the write bus bar line WI transmit the data output from the main sensing amplifier to the bit line sensing amplifier 13. The first data transmission portion 15 transmits the data output from the bit line sensing amplifier 13 to the read bus line RI and read bus bar line RI. The second data transmission portion 17 transmits the data of the write bus line WI and the write bus bar line WI to the bit line sensing amplifier 13. The first and second enable signal output portions 19 and 19a output enable signals to the bit line amplifier 13. The equalizer 21 equalizes a bit line BL and a bit bar line BL. The precharge level adjusting portion 23 adjusts precharge level of the read bus line RI and read bus bar line RI.
The first data transmission portion 15 includes first, second, third and fourth transistors TR1, TR2, TR3, and TR4. A gate of the first transistor TR1 is connected to the bit line BL and its drain is connected to the read bus line RI. A gate of the second transistor TR2 is connected to the bit bar line BL and its drain is connected to the read bus bar line RI. A source of the third transistor TR3 is connected to a ground voltage terminal Vss and its drain is connected to a source of the first transistor TR1. A column selection signal Y is applied to a gate of the third transistor TR3. A source of the fourth transistor TR4 is connected to the ground voltage terminal Vss and its drain is connected to the source of the second transistor TR2. The column selection signal Y is applied to a gate of the fourth transistor TR4.
The second data transmission portion 17 includes fifth, sixth, seventh, and eighth transistors TR5, TR6, TR7, and TR8. A drain of the fifth transistor TR5 is connected to the write bus line WI. A write enable signal WE is applied to a gate of the fifth transistor TR5. A drain of the sixth transistor TR6 is connected to the write bus bar line WI and its gate is in common connected with the gate of the fifth transistor TR5. A source of the seventh transistor TR7 is connected to the bit line BL and its drain is connected to the source of the fifth transistor TR5. The column selection signal Y is applied to a gate of the seventh transistor TR7. A source of the eighth transistor TR8 is connected to the bit bar line BL and its drain is connected to the source of the sixth transistor TR6. A gate of the eighth transistor TR8 is in common connected with the gate of the seventh transistor TR7.
The first enable signal output portion 19 outputs the enable signal to the bit line sensing amplifier 13 to maintain the bit line BL at high level completely. The first enable signal output portion 19 includes a ninth transistor TR9 which is operated by a gate input signal S0. A source of the ninth transistor TR9 is connected to the ground voltage terminal Vss.
The second enable signal output portion 19a outputs the enable signal to the bit line sensing amplifier 13 to maintain the bit line BL at low level completely. The second enable signal output portion 19a includes a tenth transistor TR10 which is operated by a gate input signal S0. A drain of the tenth transistor TR10 is connected to a power source voltage terminal Vcc.
The operation of the aforementioned conventional column selection circuit will be described below.
FIG. 2 are waveforms illustrating the operation of the conventional column selection circuit.
First, the step of transmitting data of a cell C1 to the read bus line RI and the read bus bar line RI will be described.
As shown in FIG. 2, if an equalizing signal EQ is changed from high level to low level (T1), the bit line BL and the bit bar line BL depart from equalizing state and a word line WL is changed from low level to high level (T2).
If the word line WL becomes high level, the data stored in the cell C1 are transmitted to the bit line BL as shown in FIG. 1. As a result, some voltage difference occurs between the bit line BL and the bit bar line BL.
Thereafter, a high signal is applied to the gate of the ninth transistor TR9 of the first enable signal output portion 19 (T4) (S0=high) and a low signal is applied to the gate of the tenth transistor TR10 of the second enable signal output portion 19a (T4) (S0=low). Then, as shown in FIG. 2, the bit line BL is compensated to high level completely and the bit bar line BL is compensated to low level completely. As a result, the data stored in the memory cell 11 is loaded to the bit line BL.
Voltage difference between the read bus line RI and the read bus bar line RI depending on the column selection signal is as follows.
As shown in FIG. 2, if the column selection signal Y is changed from low level to high level (T3), the third and fourth transistors TR3 and TR4 are turned on. The seventh and eighth transistors TR7 and TR8 are turned on, too.
At this time, the first transistor TR1 whose gate is connected to the bit line BL is turned on and the second transistor TR2 whose gate is connected to the bit bar line BL is turned off. This is the reason why the bit line BL is maintained at high level and the bit bar line BL is maintained at low level as the data of the cell C1 are transmitted to the bit line BL by the word line WL having high level.
Therefore, the data of the bit line BL and bit bar line BL are transmitted to the read bus line RI and read bus bar line RI.
However, if the column selection signal becomes high at the state that the bit line BL and the bit bar line BL are not completely maintained at high level and low level, respectively, the first, second, third and fourth transistors TR1, TR2, TR3 and TR4 are all turned on so that the ground voltage is applied to the read bus line RI and the read bus bar line RI.
As a result, the voltage level of the read bus line RI and read bus bar line RI becomes low.
The step of transmitting the data of the memory cell to the write bus line WI and write bus bar line WI will now be described.
As shown in FIG. 1, if the write enable signal WE and the column selection signal Y become high, the fifth, sixth, seventh and eighth transistors TR5, TR6, TR7 and TR8 are all turned on. Thus, the data of the write bus line WI and write bus bar line WI are transmitted to the bit line BL and the bit bar line BL through the turned on transistors TR5, TR6, TR7 and TR8.
At this time, since the first and second transistors TR1 and TR2 are connected to the bit line BL and the bit bar line BL, respectively, at least one of the first and second transistors TR1 and TR2 is turned on.
If the bit line BL is high level and the bit bar line BL is low level, the first transistor TR1 and the third transistor TR3 are turned on. In that case, a current path which is unnecessary is formed between the ground voltage terminal Vss and the read bus line RI. In other words, the read bus line RI is unnecessarily selected during writing the data in the memory cell.
The aforementioned conventional column selection circuit has several problems.
Since the read bus line and the write bus line are separated from each other, a layout area increases and thus the size of a chip increases. In addition, an unnecessary current path is formed by the column selection circuit for reading during data writing.